Functional Self-Test Generation for Superscalar Microprocessors

Functional testing of microprocessors has been studied for over two decades. Techniques for generating functional tests for modern microprocessors with cache/MMU and pipelining have been previously proposed [1][2]. However there are no reported techniques for automatic functional self-test generation for superscalar processors. We present such a technique that not only makes it possible to run the tests and monitor the results at native processor speeds, but also checks the performance of the superscalar mechanism. Our approach exploits the inherent processing power of the chips to compute the signature of internal processor states represented by registers, and to monitor the performance. Contrary to conventional hardware-based signature compression, there is no area overhead or performance impact. We assume the processor has a timer to check the cycle count. The technical problems handled by such an approach include the following:

• testing the branch prediction mechanism
• testing the exception and misprediction recovering mechanism
• testing the register renaming mechanism
• testing the out-of-order execution mechanism (instruction window or reservation station)
• monitoring test results using native instructions only

We have implemented a framework called TestGen. It automatically generates comprehensive functional tests for the superscalar mechanism based on the high level architectural specification. It integrates a number of technologies, including the following:

• Branch sequence generation. The algorithm generates an instruction loop, free of data dependencies. In the loop, a finite number of conditional branch instructions are scheduled. During the first iteration of the loop, all the instructions are fetched into the cache, and the branch targets are also buffered if the branch-target buffering scheme is used for branch prediction. Then the chip timer is turned on, as shown in Figure 1. The technique checks not only the final results of the sequence, but also the elapsed cycles.
• Misprediction/exception sequence generation. (1) Misprediction sequences are generated similar to the above branch sequence, except that at least one branch in the loop changes from being taken to not taken, or vice versa, during each iteration of the outer loop. (2) Exceptions are synchronous events which are responses of the processor to certain conditions during the execution of an instruction. A set of instruction sequences of a specific length can be constructed, enumerating the cases of instructions incurring exceptions interleaved with other instructions. In the exception handler, the results of other instructions are checked.
• Data dependent sequence generation. This technique generates instruction sequences of the length of the instruction window or the reservation stations, preceded by some filler code that fills the pipelines. Multiple combinations of data hazards (RAW, WAR, WAW) are enumerated in a set of test sequences. The instruction sequences are designed to detect wrong results due to defects in the register renaming logic. Also, the internal timer is used to monitor the performance of out-of-order issue/completion logic.
• Pairable instruction sequence generation. According to the instruction pairing rule of the chip's pipelines, instructions are grouped in terms of the pipelines in which they can reside, their latencies and use of resources. Pairable instructions are enumerated, and the sequence is free of data and procedural dependencies. The internal timer can be used to check the cycle count to detect performance degradation of the instruction dispatching logic.
• Native mode signature compression. The execution results of a test program are stored in multiple registers, and a signature compression routine is inserted into the test sequence systematically to compress the register values. At the end of the test, the signature is checked. Different characteristic polynomials can be used, which provides flexibility and reduces the probability of aliasing.

We have applied TestGen to the Intel Pentium processor. For example, it generates tests for the Pentium instruction pairing mechanism. The Pentium processor has two integer pipelines U and V. The U pipe is fully capable of executing any integer instruction. The V pipe can only execute simple instructions. When two simple instructions are adjacent in the instruction window or reservation station, and several rules are met, the two instructions get executed at the same time in the two pipelines. The number of test cases are shown in the following table. Both the results and execution time are checked at the end of the test sequences.

Pentium test target	Number of test cases
Integer instruction pairing mechanism	625
Floating point instruction pairing mechanism	21

The methodology has a wide range of applications, including the following:

• Tester-based manufacturing testing.
• Native mode self-test. This can be either during manufacturing testing or testing in the field. Since the functional tests can be executed at the operating frequencies, it is very effective in finding real defects [3].
• Design validation. RTL simulation or emulation is used early in the production process. The verification coverage can be measured, if the RTL code is available, based on extracted control flow information [4].

References

[1] A.J. van de Goor; & Th.J.W. Verhallen. " Functional Testing of Current Microprocessors (applied to the Intel i860) ", Proc. Intl. Test Conf., pages 684-695, 1992.

[2] D.C. Lee; & D.P. Siewiorek. " Functional Test Generation for Pipelined Computer Implementations", FTCS, pages 60-67, 1991.

[3] P.C. Maxwell; R.C. Aitken; V. Johnson; & I. Chiang. "The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?", Proc. Intl. Test Conf., pages 358-364, 1991.

[4] D. Moundanos; J. A. Abraham; & Y. V. Hoskote. "Abstraction Techniques for Validation Coverage Analysis and Test Generation", IEEE Trans. on Computers, Vol. 47, No.1, pages 2-14, 1997.

1. Author contact: Computer Engineering Research Center, the University of Texas at Austin., Austin, TX 78712. Phone: (512)471-8012. Fax: (512)471-8967. E-Mail: jshen@cerc.utexas.edu. The work is sponsored by the Texas Advanced Technology Project 003658-268 and a grant from Intel Corporation.