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Introduction
The fault injection is a technique of validating Fault Tolerant Systems (FTSs) which is being increasingly consolidated and applied in a wide range of fields, and several automatic tools have been designed [Clark,95].
A very desirable objective in the process of designing FTSs, is to couple tightly the fault injection-based validation and design tasks. In this way, the inclusion of Fault Tolerant Mechanisms in the design of a system can be optimized. The development of integrated and coherent design mechanisms of Fault Tolerant Systems seems reachable if the emergence of the Hardware Description Languages is taken into account. In this context, VHDL has been recognised as a very useful language, because it presents the following interesting features:
· Possibility of describing both the structure and the behaviour of a system as a unique syntactic element.
· Wide diffusion in the present digital design, and inherent capability to perform hierarchical descriptions on different abstraction levels [Dewey,92] [Aylor,90].
· Good performance in the modelling of digital systems at high level.
· Capability to support test activities [Miczo,90].
The injection tool
We have developed an injection tool for automatic fault injection in VHDL models at gate-level, register-level and chip-level.
The general structure of the injection tool is shown in the block diagram of figure 1. It is composed by a series of elements designed around a commercial VHDL simulator. A detailed description can be seen in [Dgil,97].
Configuration file
Fault injection experiments are defined in a file using the following parameters:
1. Experiment name.
2. Total number of injected faults.
3. Fault injection time instant.
4. Fault duration (transient faults).
5. Places (signals/variables) where faults are injected.
6. Fault value.
7. Output file: result.
Macro generator
This is a program that writes a file with calls the macros that perform the injection. The parameters for the macros are defined in the configuration file so that they can vary from one experiment to another. The macros have been written by the command-language of the simulator.
Simulator
It has been used the commercial VHDL simulator V-System/Windows by Model Technology [Model,97] for IBM-PC (or compatible). It is a simple and easy to use event-driven simulator. When activated by the user, the simulator executes the file with macros and generates the output text file .lst for every injection. The .lst file contains the trace of the whole simulation.
Data analyser
This program analyses the output file .lst for each injection, and compares it to the reference fault-free output file to provide the following information: type of the injected fault, type of error, latencies (propagation, detection, recovery) and coverage (detection, recovery). The results of the comparison are stored in the file result.
VHDL component library
It is a set of VHDL models used to build or modify models of Fault-Tolerant Systems, to be able to validate them. It has the VHDL models at gate, register or chip level.
System
It is a VHDL model to be studied/validated. The proposed tool deals with models at gate, register or chip level.
VHDL injector library
This library comprises injector models in VHDL that can be added to the system model. These models allow the injection of new faults to make available a large set of fault types. They can be applied to signals, in structural architectures of the model (short, bridging, delay or bit-flip faults). They can also be applied at algorithmic level in behavioral architectures of the model, changing the syntactical structures of the VHDL code [Armstrong,92]. They are called respectively saboteurs and mutants in [Jenn,94a].
In short, the tool is easy to use and versatile, and it is appropriate to perform injection experiments in medium complexity systems.
Future work
Nowadays, the tool is being updated to enhance the following points:
· Obtaining the list of places where the fault can be injected by a lexical and syntactic analysis of the VHDL code of the model. The place must be obtained according to the hierarchy of the model. Moreover, random or deterministic predicates (topologic, syntactic or semantic) can be imposed over the characteristics of the selected places [Jenn,94b].
· Automatic fault injection using saboteurs and mutants. Mutants may also be automatically generated from the syntactic tree of the model [Jenn,94b]. Saboteurs may be implemented by simulator commands in case the fault injection is independent of the semantic of the element under consideration. Otherwise, the insertion is done manually. The configuration of the VHDL language can be used to optimize the injection based on saboteurs and mutants, since it allows the re-utilization of perturbed elements without modifying the architectures.
· Development of the VHDL component library, with the following elements: gates, flip-flops, counters, registers, ALUs, memory modules, processors, and fault tolerant architectures.
· Improvement of the user interface.
· Reduction of the simulation time, by starting it just before the occurrence of the fault. In this way, it is not necessary to simulate the running time before the fault.
· Develop a programming language, based on the simulator commands, that covers the whole injection process. This way, experiments are processed with minimum user interaction.
· Migrate the tool to more powerful VHDL simulators. Basically, the commands used on the injection macros must be compatible among different simulators.
This tool has been used to study the error syndrome in a microcomputer system [Dgil,97]. Transient faults (stuck-at and open-line) were injected using simulator commands. The results showed the percentage of produced errors and the error latency. These data can be used to design the most suitable fault detection and tolerance mechanisms to increase the system Dependability.
References
[Armstrong,92] Armstrong J.R., Lam F.-S., Ward P.C. "Test generation and Fault Simulation for Behavioral Models". En Performance and Fault Modeling with VHDL. (J.M.Schoen ed.), pp.240-303, Englewood Cliffs, Prentice-Hall, 1992.
[Aylor,90] Aylor J.H., Williams R.D., Waxman R., Johnson B.W., Blackburn R.L. "A Fundamental Approach to Uninterpreted/Interpreted Modeling of Digital Systems in a Common Simulation Environment". Technical Report 900724.0, Univ. of Virginia, 1990.
[Clark,95] J. Clark., D. Pradhan, "Fault Injection. A method for validating computer-system dependability", IEEE. Computer, June 1995.
[Dgil,97] D. Gil, J. C. Baraza, J. V. Busquets, P. J. Gil. "Fault Injection with simulation in VHDL and application to a simple microcomputer system". Proceedings of the ADCOMP’97 (5th IEEE International Conference on Advanced Computing). pp 466-474. Chennai, India. December 1997.
[Dewey,92] Dewey A., Geus A.J.D. "VHDL: Toward a Unified View of Design". IEEE Design and Test of Computers, pp.8-17, 1992.
[Jenn,94a] Jenn E., Arlat J., Rimen M., Ohlsson J., Karlsson J. "Fault Injection into VHDL Models: The MEFISTO Tool", FTCS-24, IEEE, 1994, pp. 66-75.
[Jenn,94b] E. Jenn, "Sur la validation des systèmes tolérant les fautes: injection de fautes dans des modèles de simulation VHDL", Thèse, Rapport LAAS nº 94361, 1994.
[Miczo,90] Miczo A. "VHDL as a Modeling-for-Testability Tool". En Proceedings COMPCON'90, pp.403-409, 1990.
[Model,97] Model Technology, "V-System/PLUS PC User´s Manual. Version 4.6", 1997.