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ISSRE
2003
ISSRE 2002
ISSRE
2001
ISSRE 2000
ISSRE 1999
ISSRE 1998
FTCS
1999
FTCS 1998
PROCEEDINGS FROM 1971 FTCS
CONTENTS
SESSION I: TEST GENERATION & DIAGNOSIS
Chairman: E. J. McCluskey, Stanford University,
Stanford, California
1. On the Design of Minimum Length Fault Tests for Combinational Circuits
L. W. Bearnson and C. C. Carroll.............................................................1
2. Algorithms for Detection of Faults in Logic Circuits
W. G. Bouricius, B. P. Hsieh, G. R. Putzolu, J. P. Roth, P. R.
Schneider and C. J. Tan.......5
3. Boolean Difference
for Fault-Detection in Asynchronous Sequential Machines
M. Y. Hsiao and D. R.Chia....................................................................9
4. An Efficient Algorithm for Generating Complete Test Sets for Combinational
Logic Circuits
S.S. Yau and Y. S. Tang.....................................................................14
5. Generation of Fault Detection Tests for Sequential Circuits
M. A. Breuer.............................................................18
6. Diagnosable Machine Realizations of Sequential Behavior
J. F. Meyer and K. Yeh......................................................................22
SESSION II: FAULT-LOCATION & TESTING
Chairman: W. H. Kautz, Stanford Research Institute, Menlo Park, California
1. A Graph Theoretical and Probabilistic Approach to the Fault
Detection of
Digital Circuits
J. C. Rault ........................................................................26
2. Locatability
of Faults in Abstract Networks
F. G. Gray and J. F. Meyer..................................................................30
3. Structural Factors in the Fault Diagnosis of Combinational Networks
J. D. Russell and C. R. Rime ...............................................................34
4. Cause-Effect Analysis for Multiple Fault Detection in Combinational
Networks
D. C. Bossen and S. J. Hong. ...............................................................40
5. The Algebraic Approach to Faulty Logic Networks
F. W. Clegg and E. J. McCluskey ...........................................................
44
6. On the Design of Multiple Fault Diagnosable Networks
G. Metze and D. R. Schertz .................................................................46
PANEL SESSION: DIAGNOSIS & TESTING
Chairman: Stephen A. Szygenda, Southern Methodist University,
Dallas, Texas
1. Problems Associated With the Implementation and Utilization of
Digital Simulators
and Diagnostic Test Generation Systems
S. A. Szygenda ..................................................51
2. Testing and Diagnosing - A Practitioner's Point of View
J. J. Dent...............................................53
3. Diagnosing and Testing, Aerospace Digital Computers
E. F. Meyers .....................................................................55
4. Increasing System Availability By Using On Line Test and Diagnosing
P. J. Scola ......................................................................58
5. (The papers of the following panel members were not received in time
for publication)
H. Mays
E.J. McCluskey
L.S. Tuomenoksa
SESSION III: RELIABILITY MODELING & ANALYSIS
Chairman: W. G. Bouricius, IBM Research Center, Yorktown Heights, New
York
1. Reliability Modeling for Fault-Tolerant Computers
W. G. Bouricius, W. C. Carter, D. C. Jessep, P. R. Schneider and A. B.
Ladle................60
2. Analysis of Parallel Systems
T. B. Bredt .......................................................................64
3. A Method for Redundancy Scheme Performance Assessment
T. F. Klaschka.........................................................69
4. Diagnostic Results of Field Test of PLATON Switching System
J. Gillot and P. Grall .....................................................................74
5. Reliability Modeling, Analysis and Prediction of Ultra reliable
Fault-Tolerant
Digital Systems
F.P. Mathur ..................................................... 79
SESSION IV: ARCHITECTURE & DESIGN
Chairman: F. P. Mathur, Jet Propulsion Laboratory, Pasadena, California
1. A Theory of Design of Fault-Tolerant Computers Using Standby Sparing
W. C. Carter, W. G. Bouricius, D. C. Jessep, J. P. Roth,
P. R. Schneider,
A. B. Wadia.......83
2. The MECRA, A Self-Reconfigurable Computer for Highly Reliable Process
F. P. Maison ....................................................................87
3 The STAR (Self-Testing-And-Repairing) Computer: An Investigation
of the Theory
and Practice
of Fault-Tolerant Computer Design
A. Avizienis, G. C. Gilley, F. P. Mathur, D. A. Rennels, J. A. Rohr and
D. R. Rubin ........92
4. A Fault-Tolerant Information Processing Concept for Space Vehicles
A. L. Hopkins, Jr ..........................................................................97
5. A Three-Failure Tolerant Computer System
L. J. Koczela ......................................................................101
SESSION V: ERROR PROTECTION & RECOVERY
Chairman: G. Metze, University of Illinois, Urbana, Illinois
1. A Log-Out Analysis Method for Fault Detection in Computer
D.D. Cheng ...........................................................
1O5
2. Error Switch of Duplicated Processor in the No. 2 Electronic
Switching System
W. N. Toy .........................................................108
3. Logic Design for Dynamic and Interactive Recovery
W.C. Carter, D.C. Jessep, A.B. Wadis, P.R. Schneider and W.G. Bouricius
...................110
4. Realization of Fail-Safe Sequential Machines by Using K-out-of-N Code
Y. Tohma, Y. Ohyama and R. Sakai ..........................................................114
5. Arithmetic Error Codes: Coat and Effectiveness Studies for
pplication in
Digital System Design
A. Avizienis ......................................................118
6. Computer System Diagnosis Using Teat Gates Method
W. Mayeda and C. V. Ramamoorthy ...........................................................122
SESSION VI: SOFTWARE RELIABILITY
Co-Chairmen: B. Elspas & R. N. Levitt, Stanford Research Institute,
Menlo Park, California
1. Software Reliability Through Proving Programs Correct
R.L. London .....................................................................125
2. Proving Programs to be Correct
J. C. Ring ........................................................................130
3. Prevention of Deadlocks in Multiprocessing Supervisory Software
P. G. Hebalkar .......................................................................134
4. Program Correctness, Software Reliability, and Todays Capabilities
R. B. Mulock .......................................................................137
5. A Comparison of Formal Program Validation Techniques
B. Elspas, R. N. Levitt, A. Waksman and R. Waldinger ......................................140
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