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FTCS-22
The Twenty-Second Annual International Symposium on Fault-Tolerant Computing
July 8-10, 1992
Boston, Massachusetts, USA
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Protecting Processing Elements in Communications Satellites
R.Redinbo pg.8
Replicated Distributed Processes in Manetho
E.N. Elnozahy and W. Zwaenepoel pg.18
Active Replication in Delta-4
M. Chereque, D.Powell, R. Reynier, J.L. Richier, and J. Voiron pg.28
Design for Fault Tolerance in System ES/9000 Model 900
L. Spainhower, J. Isenberg, R. Chillarege, and J. Berding pg.38
Dynamic Reconfiguration of CSP Plograms for Fault Tolerance
P. Jalote pg.50
Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs
R. Karri and A. Orailoglu pg.57
Compiler-Assisted Static Checkpoint Insertion
J. Long, W.K. Fuchs, and J.A. Abraham pg.58
Branch Recovery with Compiler-Assisted Multiple Instruction Retry
N.J. Alewine, S.K. Chen, C.C. Li, W.K. Fuchs, and W.M. Hwu pg.66
Transis: A Communication Subsystem for High Availability
Y. Amir, D. Dolev, S. Kramer, and D. Malki pg.76
A Posteriori Agreement for Fault-Tolerant clock Synchronization on Broadcast Networks
P. Verissimo and L. Rodrigues pg.85
Fault-Tolerant Real-Time Communication in Distributed Computing Systems
Q. Zheng and K.G. Shin pg.86
Design of Fully Exercised SFS/SCD Logic Networks
T. Nanya, S. Hatakenaka and R. Onoo pg.96
Design of Static CMOS Self-Checking Circuits Using Built-In Current Sensing
J.C. Lo, J.C. Daly, and M. Nicolaidis pg.104
Multiple Signature Analysis: A Framework for Built-In Self-Diagnostic
M.G. Karpovsky, S.M. Chaudhry, and L.B. Levitin pg.112
Design and Analysis of Multibus Systems Using Projective Geometry
D. Bulka and J.B. Dugan pg.122
Uniformization and Exponential Transformation: Techniques for Fast Simulation of Highly Dependable Non-Markovian Systems
V.F. Nicola, P. Heidelberger, and P. Shahabuddin pg.130
Design and Modeling of Clustered RAID
A. Merchant and P S. Yu pg.140
Fast Simulation of Markovian Reliability/Availability Models with General Repair Policies
S. Juneja and P. Shahabuddin pg.150
Efficient Fault-Tolerant Mesh and Hypercube Architectures
J. Bruck, R.Cypher, and C.T. Ho pg.162
Free Dimensions - An Effective Approach to Achieving Fault Tolerance in Hypercubes
C.S. Raghavendra, P.J. Yang , and S.B. Tien pg.170
Optimal Ring Embedding in Hypercubes with Faulty Links
S. Latifi, S.Q. Zheng, and N. Bagherzadeh pg.178
Routing in Modular Fault-Tolerant Multiprocessor Systems
M.S. Alam and R.G. Melhem pg.185
Performance Bounds in List Scheduling of Redundant Tasks on Multiprocessors
D.T. Peng pg.196
Scheduling Message Processing for Reducing Rollback Propagation
Y.M. Wang and W.K. Fuchs pg.204
Reliability Modeling of Large Fault-Tolerant Systems
N. Suri, N.M. Hugue, and C.J. Walter pg.212
Models for Time Coalescence in Event Logs
J.P. Hansen and D.P. Siewiorek pg.221
A Divide-and-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits
I. Pomeranz and S.M. Reddy pg.230
Finite State Machine Testing Based on Growth and Disappearance Faults
M.K. Srinivas, J. Jacob, and V.D. Agrawal pg.238
An Efficient Test Generation Algorithm Based on Search State Dominance
T. Fujino and H. Fujiwara pg.246
Testing with Correlated Test Vectors
S. Bou-Ghazale and P.N. Marinos pg.254
Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults
S. Kajihara, H. Shiba, and K. Kinoshita pg.263
Incorporating Testability Considerations in High-Level Synthesis
A. Mujumdar, K. Saluja, and R. Jain pg.272
Synthesis of Multilevel Combinational Circuits for Complete Robust Path Delay Fault Testability
N.K. Jha, I. Pomeranz, S.M. Reddy, and R J. Miller pg.280
A Structural Technique for Fault Protection in Asynchronous Interfaces
A.V. Yakovlev pg.288
On Combining Off-Line BIST and On-Line Control Flow Checking
B. Eschermann pg.298
Direct Methods for Synthesis of Self-Monitoring State Machines
S.W.Robinson and J.P. Shen pg.306
A Study of the Effects of Transient Fault Injection into a 32-Bit RISC with Built-In Watchdog
J. Ohlsson, M. Rimen,and U. Gunneflo pg.316
Two Software Techniques for On-Line Error Detection
G. Miremadi, J. Karlsson, U. Gunneflo, and J. Torin pg.328
FERRARI: A Tool for the Validation of System Dependability Properties
G.A. Kanawati, N.A. Kanawati, and J.A. Abraham pg.336
Fault Injection for the Formal Testing of Fault Tolerance
D. Avresky, J. Arlat, J.C. Laprie, and Y. Crouzet pg.345
A New Statistical Approach for Fault-Tolerant VLSI System
C.H. Stapper pg.356
Chip Test Optimization Using Defect Clustering Information A.D. Singh and C.M. Krishna pg.366
Wafer Testing with Pairwise Comparisons
K. Huang, V.K. Agarwal, L. LaForge, and K. Thulasiraman pg.374
Failure Mode Assumptions and Assumption Coverage
D. Powell pg.386
Closure and Convergence: A Formulation of Fault-Tolerant Computing
A. Arora and M. Gouda pg.396
Optimal Algorithms for Exact, Inexact, and Approval Voting B. Parhami pg.404
Fault-Tolerant Neural Networks in Optimization Problems
Y. Koyanagi and Y. Tohma pg.412
Protecting Practical FFT ImplementaLions that Share Common Processing Elements
J. Sung and R. Redinbo pg.420
More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication
F.T. Assaad and S. Dutt pg.430
Efficient Utilization of Spare Capacity for Fault Detection and Location in Multiprocessor Systems
S. Tridandapani and A K. Somani pg.440
Design and Analysis of Software Reconfiguration Strategies for Hypercube Multicomputers under Multiple Faults
M. Peercy ant P. Banerjee pg.448
Outage Times in Fault-Tolerant Systems
A. Reibman pg.458
Recovery/Serviceability System Test Improvements for the IBM ES/9000 520-Based Models
A.C. Merenda and E. Merenda pg.463
Latent Design Faults in the Development of Multiflow's TRACE/200
R.P. Colwell pg.468
A Comparison of Software Defects in Database Management Systems and Operating Systems
M. Sullivan and R. Chillarege pg.475
Unordered Error-Correcting Codes and Their Applications
M. Blaum and J. Bruck pg.486
Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems
E. Fujiwara ant M. Hamada pg.494
Efficient Multiple Unidirectional Byte Error-Detecting Codes for Computer Memory Systems
T.R.N. Rao, G.L. Feng, and M.S. Kolluru pg.502
Improved Construction Methods for Error Correcting Constant Weight Codes
S. Al-Bassam, C. Ramanathan, and B. Bose pg.510