FTCS-26:

The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing

Sendai International Center
Sendai, Japan, June 25-27, 1996

Tuesday, June 25, 1996
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9:15 - 9:45 Opening Remarks

9:45 - 10:15 Keynote Address

"The Evolution of Information Network Society and the Dependability
in the 21st Century,"
Shoichi Noguchi, Nihon Univ., Japan

10:15 - 10:45 Coffee break

10:45 - 12:15 Panel 1: Availability of Commercial Parallel Systems
Moderator: Jen-Yao Chung,
IBM Thomas J. Watson Research Center, USA

12:15 - 13:30 Lunch

13:30 - 15:00 Parallel sessions

Session A1 - Distributed Systems


1."Reconfiguration and Transient Recovery in State-Machine
Architectures,"
J.Rushby, SRI International, USA

2."Recovery in Mobile Environments: Design and Trade-Off Analysis,"
D. K.Pradhan, P. Krishna, N. H. Vaidya, Texas A&M Univ., USA

3."Evaluating Quorum Systems over the Internet,"
Y. Amir, John Hopkins Univ.,USA; A. Wool, Weizmann Institute, Israel

Session B1 - Testing

1."A Fault Simulation Method for Crosstalk Faults in Synchronous
Sequential Circuits,"
N. Itazaki, Y. Idomoto, K. Kinoshita, Osaka Univ., Japan

2."Random Pattern Testing for Sequential Circuits Revisited,"
L.Nachman, K.K. Saluja, Univ. of Wisconsin, USA;
S. Upadhyaya, R.Reuse, SUNY at Buffalo, USA

3."Dynamic Test Compaction for Synchronous Sequential Circuits using
Static Compaction Techniques,"
I. Pomeranz, S. M. Reddy, Univ. of Iowa, USA

15:00 - 15:30 Coffee break

15:30 - 16:30 Parallel sessions

Session A2 - File Systems

1."FT-NFS: An Efficient Fault Tolerant NFS Server Designed for
Off-the-Shelf Workstations,"
N. Peyrouze, G. Muller, IRISA-INRIA, France

2."Design and Evaluation of Fault-Tolerant Shared File System for
Cluster Systems,"
S. Sumimoto, Fujitsu Laboratories Ltd., Japan

Session B2 - Diagnosis

1."Multiple Fault Diagnosis in Sequential Circuits using Sensitizing
Sequence Pairs,"
N. Yanagida, H. Takahashi, Y. Takamatsu, Ehime Univ., Japan

2."Fault Diagnosis using State Informations,"
V. Boppana, I. Hartanto, W. K. Fuchs,
Univ. of Illinois at Urbana-Champain, USA

16:30 - 17:30 Parallel sessions

Session A3 - Evaluation

1."Modeling the Dependability of the French Air Traffic Control System,"
K.Kanoun, M. Borrel, LAAS-CNRS, France;
T. Morteveille, SRTI System, France; A. Peytavin, CENA, France

2."A New Methodology for Calculating Distributions of Reward Accumulated
during a Finite Interval,"
M. A. Qureshi, W. H. Sanders, Univ. of Illinois at Urbana-Champain,
USA

Session B3 - On-Line Checking

1."Algebraic Techniques for the Optimization of Control Flow Checking,"
G.Noubir, B. Y. Choueiry, EPFL, Switzerland

2."Executable Assertions and Timed-Traces for On-Line Software Error
Detection,"
C. Rabejac, J.-P. Blanquart, Matra Marconi Space and LIS, France;
J.-P. Queille, Matra Marconi Space, France

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Wednesday, June 26, 1996
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8:30 - 10:00 Panel 2: Dependability of Railway Control Systems
Moderators: Jean Arlat, LAAS-CNRS, France;
Nobuyasu Kanekawa, Hitachi, Ltd., Japan

10:00 - 10:30 Coffee break

10:30 - 12:00 Parallel sessions

Session A4 - Group Communication

1."A Multiple Bus Broadcast Protocol Resilient to Non-Cooperative
Byzantine Faults,"
K. Echtle, A. Masum, Univ. Essen, Germany

2."Consensus Service: A Modular Approach for Building Agreement
Protocols in Distributed System,"
R. Guerraoui, A. Schiper, EPFL, Switzerland

3."Group, Majority and Strict Agreement in Timed Asynchronous Distributed
Systems,"
F. Cristian, Univ. of California, San Diego, USA

Session B4 - Coding

1."Optimal Two-Level Byte Error Protection Codes for Computer Systems,"
T.Ritthongpitak, M. Kitakami, E. Fujiwara, Tokyo Int. of Tech., Japan

2."Symbol Error Correcting Codes for Memory Applications,"
C. L. Chen, IBM Corp., USA

3."Limitations of VLSI Implementation of Delay-Insensitive Codes,"
V. Akella, Univ. of California, Davis, USA;
N.H. Vaidya, Texas A & M University, USA;
R. Redinbo, Univ. of California, Davis, USA

12:00 - 13:15 Lunch

13:15 - 14:15 Parallel sessions

Session A5 - Verification & Testing

1."Verification of Fault-Tolerance and Real-Time,"
Z. Liu, Univ. of Leicester, United Kingdom;
M. Joseph, Univ. of Warwick, United Kingdom

2."A Framework for Conformance Testing of Systems Communicating through
Rendezvous,"
Q. M. Tan, A. Petrenko, G. v. Bochmann, Univ. de Montreal, Canada

Session B5 - Design

1."Mitigating Operator-Induced Unavailability by Matching Imprecise
Queries,"
R. A. Maxion, P.A. Syme, Carnegie Mellon Univ., USA

2."Supporting Nondeterministic Execution in Fault-Tolerant Systems,"
J. H. Slye, E. N. Elnozahy, Carnegie Mellon Univ., USA

14:30 - 18:00 Excursion

19:00 - 21:00 Banquet

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Thursday, June 27, 1996
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8:30 - 10:00 Parallel sessions

Session A6 - Networks

1."Reliable Broadcasting in Product Networks with Byzantine Faults,"
F. Bao, Y. Igarashi, Gunma Univ., Japan

2."Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track
Fault-Tolerant Designs for Mesh-Connected Multicomputers,"
N. R. Mahapatra, S.Dutt, Univ. of Minnesota, USA

3."Spare Processor Allocation for the Fault-Tolerance in Torus-Based
Multicomputers,"
M. M. Bae, B. Bose, Oregon State Univ., USA

Session B6 - Experiment & Analysis

1."A Comparative Analysis of Event Tupling Schemes,"
M. F. Buckley, IBM Research Division, Hawthorne;
D. P. Siewiorek, Carnegie Mellon Univ., USA

2."Generation of an Error Set that Emulates Software Faults - Based on
Field Data,"
J. Christmansson, Chalmers Univ. of Tech., Sweden;
R. Chillarege, IBM Thomas J. Watson Research Center, USA

3."An Approach towards Benchmarking of Fault-Tolerant Commercial
Systems,"
T.K. Tsai, R. K. Iyer, Univ. of Illinois at Urbana-Champain, USA

10:00 - 10:30 Coffee break

10:30 - 11:30 Parallel sessions

Session A7 - Self-Checking

1."The Design of Totally Self-Checking Checkers for Some Classes of
Hadamard Codes,"
N. Wakita, Toshiba Co., Japan; K. Takagi,Y. Iwadare, Nagoya
Univ.,Japan

2."Behavioral Synthesis of Fault Secure Controller/Datapaths using
Aliasing Probability Analysis,"
G. Lakshminarayana, A. Raghunathan, N. Ja, Princeton Univ., USA

Session B7 - Practical Experience Reports 1

1."Efficient Service of Rediscovered Software Problems,"
I. Lee and G. Pitt, Tandem Computers Inc., USA

2."Formal Methods for the Validation of Autonomous Spacecraft Fault
Tolerance,"
R. Gerlich, Dornier Gmbh, Germany;
S.Ayache, P. Humbert, Matra Marconi Space, France;
E. Conquet, C. Rodriguez, VERIMAG, France;
J.Sifakis, IMAG - LGI, France

11:30 - 12:30 Parallel sessions

Session A8 - Parallelization

1."Compiler Assisted Generation of Error Detecting Parallel Programs,"
A.Roy-Chowdhury, IBM Thomas J. Watson Research Center, USA;
P. Banerjee, Univ. of Illinois at Urbana-Champain, USA

2."Efficient Checkpoint Mechanisms for Massively Parallel Machines,"
T.Chiueh, P. Deng, SUNY at Stony Brook, USA

Session B8 - Practical Experience Reports 2

1."The Redundancy of the Ariane 5 Operational Control Center,"
J.-L. Dega, Matra Marconi Space, France

2."Highly Available Directory Services in DCE,"
B. Acevedo, L. Bahler, Bellcore, USA;
E.N. Elnozahy, Carnegie Mellon Univ., USA;
V. Ratan, M. E. Segal, Bellcore, USA

12:30 - 13:45 Lunch

13:45 - 15:15 Parallel sessions

Session A9 - Fault Injection

1."Experimental Evaluation of the Fail-Silent Behavior in Programs with
Consistency Checks,"
M. Z. Rela, H. Madeira, J. G. Silva, Univ. of Coimbra, Portugal

2."Testing of Fault-Tolerant and Real-Time Distributed Systems via
Protocol Fault Injection,"
S. Dawson, F. Jahanian, T. Mitton, T.-L. Tung, Univ. of Michigan, USA

3."Experimental Assessment of Parallel Systems,"
J. G. Silva, J. Carreira, H. Madeira, D. Costa, F. Moreira,
Univ. of Coimbra, Portugal

Session B9 - Practical Experience Reports 3

1."Self-Checking and Fail-Safe LSIs by Intra-Chip Redundancy,"
N. Kanekawa, M. Nohmi, H. Satoh, Y. Satoh, Hitachi Ltd., Japan

2."Technologies on Designing Dependable A/D Converters,"
K. Kawamura, T.Matsubara, Y. Koga, National Defense Academy, Japan

3."Two Error Detecting and Correcting Circuits for Space Applications,"
R. Johansson, Saab Ericsson Space, Sweden

15:30 - 17:00 Fault-Tolerant Computing Technical Committee Meeting